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Freescale Semiconductor /MK61F15WS /DDR /CR27

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Interpret as CR27

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PLEN 0RESERVED0 (0)PRIEN 0RESERVED0 (0)RWEN 0RESERVED0 (0)SWPEN 0RESERVED

SWPEN=0, RWEN=0, PRIEN=0, PLEN=0

Description

DDR Control Register 27

Fields

PLEN

Placement Enable

0 (0): Disabled. The command queue is a straight FIFO.

1 (1): Enabled. The command queue is filled according to the placement logic factors.
RESERVED

Reserved
PRIEN

Priority Enable

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved
RWEN

Read Write same Enable

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved
SWPEN

Swap Enable

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data